Fixed transconductance bias apparatus
US6400185B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Feb 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A transconductance bias circuit includes: a differential pair having a first transistor M14 and a second transistor M15; a resistor R coupled between a gate of the first transistor M14 and a gate of the second transistor M15, the gate of the first transistor M14 is coupled to a reference voltage node; a third transistor M10 coupled to the first transistor M14; a fourth transistor M11 coupled to the second transistor M15; a fifth transistor M8 coupled to the third transistor M10, a gate of the fifth transistor M8 is coupled to the reference voltage node; a sixth transistor M9 coupled to the fourth transistor M11, a gate of the sixth transistor M9 is coupled to the reference voltage node; a current mirror 22 coupled to the fifth and sixth transistors M8 and M9; and a seventh transistor M6 coupled to the fourth transistor M11, a current in the seventh transistor M6 is equal to a current in the resistor R.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.