Semiconductor integrated circuit, liquid crystal apparatus, electronic apparatus and method for testing semiconductor integrated circuit
US6400196B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jul 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor integrated circuit has a reset signal generation circuit (10) that generates a reset signal (12) having a reset period based on a power-on reset signal (11), and a latch circuit (20) having an initialization circuit (23) that initializes a latch output (21) based on the reset signal (12). The reset signal generation circuit (10) has a delay circuit (14) that can variably set a pulse width corresponding to the reset period of the reset signal (12). An output line of the delay circuit (14) is connected to a first pad terminal (32). An output line of the initialization circuit (23) is connected to a second pad terminal (34). When the semiconductor integrated circuit is verified, the first and second pad terminals (32, 34) are brought in contact with a probe (40). During this verification process, according to input/output loads of a tester that is connected to the first pad terminal (32), the pulse width of the reset signal (12) is set wider than that during the normal use when the pad terminals are not contacted with a probe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.