Delay device having a delay lock loop and method of calibration thereof
US6400197B2 · kind B2 · utility
25Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jan 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.