Graphics processor architecture employing variable refresh rates
US6400361B2 · kind B2 · utility
8Cited by
10References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 23, 1998 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Apr 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The display system includes a display controller which renders text and graphics and writes it to the RAM. The display controller then reads the rendered information from the RAM and activates a display based upon that information. Generally the display controller reads information from the display controller and activates the display at a constant refresh rate; however, when a large number of text and/or graphics to be rendered have accumulated, the display controller temporarily reduces the refresh rate in order to render and write the text and/or graphics to the RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.