Cache memory cell with a pre-programmed state
US6400599B1 · kind B1 · utility
3Cited by
9References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 12, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data read into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.