Method and system for pulse shaping in test and program modes
US6400605B1 · kind B1 · utility
24Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 30, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | May 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a single input pin on an integrated circuit chip that serves multiple functions during normal, test, and program modes. A first voltage detector detects a first predetermined high voltage level to place an integrated circuit in test mode. A second voltage detector detects a second predetermined high voltage level to place the integrated circuit in program mode. A high level switch is triggered to activate a pulse shaping circuit, which ramps up voltage gradually to prevent causing damage to programmable cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.