Semiconductor memory device and method of checking same for defect
US6400621B2 · kind B2 · utility
65Cited by
23References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jul 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.