Semiconductor memory device
US6400628B2 · kind B2 · utility
2Cited by
2References
11Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 27, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Dec 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dummy bit line is formed from the same layer as and separately from a bit line, and is running in parallel with the bit line. Capacitor is formed on the layer upper than bit line and has a cell plate. An intermediate interconnection is formed on the layer upper than capacitor and is electrically connected to cell plate and dummy bit line. Thus, a semiconductor memory device is obtained in which a cell plate voltage can reliably be fed to a cell plate while preventing the increase of the area of a chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.