Method and apparatus for a fault tolerant, software transparent and high data integrity extension to a backplane bus or interconnect
US6400682B1 · kind B1 · utility
23Cited by
14References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/14
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.