Fairness scheme for a serial interface
US6400725B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1998 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Dec 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/417
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
To maximize the throughput and minimize the latency associated with communications among devices on a single channel communications system, this invention provides a method and apparatus for a fairness based protocol that assures each device an equal opportunity to access the single channel communications system. The protocol forces a “fairness” delay between each sequential transmission from a device, thereby allowing another device to gain access to the communications channel during this fairness delay period. In a preferred embodiment, the duration of each transmission is limited, thereby providing a maximum latency period for a device to gain access to the communications channel, and a minimum bandwidth allocation to the device. By providing a protocol having a guaranteed minimum bandwidth and maximum latency, a device in accordance with this invention need only contain the storage resources needed for the latency period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.