Apparatus and method for an error signal compression technique in a fast adaptive equalizer circuit
US6400760B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1998 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Oct 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a transceiver unit including an adaptive equalizer filter unit, apparatus is provided for reducing or compressing the number of bits representing an error signal. The apparatus replaces a plurality of the most significant logic signal bits with a single bits while transferring the sign logic signal bit and the logic signal bits of lesser significance unchanged. Because of the reduction in the number of logic signal bits, the number of components implementing the multiplier unit in the adaptive filter unit can be reduced (i.e., in each stage of the adaptive filter). The reduction of the apparatus implementing the processing the error signal results in the same equilibrium value of the error signal, however, the time to reach this equilibrium value is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.