Driver circuit for a high speed transceiver
US6400771B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 1998 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jul 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0292
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention is generally directed to a driver circuit for a high speed transceiver. In accordance with one aspect of the invention, the driver circuit includes a first driver segment disposed to receive a control signal and configured to drive the control signal from a logic zero state to a logic one state and place the driven signal on a first driver segment output. Similarly, the driver circuit includes a second driver segment disposed to receive the control signal and configured to drive the control signal from a logic one state to a logic zero state and place the driven signal on a second driver segment output. In this regard, the control signal is a signal generated internally (i.e., within the chip) to be driven across a bus to another chip. The strength of the control signal must be increased before driving the control signal onto the bus. For this reason, the first driver segment and the second driver segment each include a plurality of drive units that are disposed in a cascaded configuration. As the control signal passes through each successive drive unit, it gains in signal strength. As will be appreciated by persons skilled in the art, this cascaded drive unit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.