Shared write buffer for use by multiple processor units
US6401175B1 · kind B1 · utility
12Cited by
9References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared write back buffer for storing data from a data cache to be written back to memory. The shared write back buffer includes a plurality of ports, each port being associated with one of a plurality of processing units. All processing units in the plurality share the write back buffer. The shared write back buffer further includes a data register for storing data provided through the input ports, an address register for storing addresses associated with the data provided through the input ports, and a single output port for providing the data to the associated addresses in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.