Parallel computing units having special registers storing large bit widths
US6401190B1 · kind B1 · utility
21Cited by
6References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1997 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Sep 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.