Data processor system having branch control and method thereof
US6401196B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1998 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jun 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.