Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden
US6401212B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system (10) embodiment, there is included a memory (18) and circuitry (16a) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (14), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (16b, 16n, 17) using the system resource. The system further includes circuitry (20, 22, 24) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (26) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.