Method of forming fully self-aligned TFT with improved process window
US6403407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Jun 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A method for opening resist in raised areas of a semiconductor device. In one aspect, a conductive layer is formed over a channel insulator layer to form a raised portion including a height above a substantially planar surrounding area, the channel insulator layer being aligned to a gate electrode. A photoresist layer is formed over the raised portion and the surrounding area, and patterned by employing a gray scale light mask to reduce exposure light on the photoresist over the raised portion. Then, the photoresist is etched to thin it such that a gap is formed in the photoresist down to the conductive layer over the raised portion, but the photoresist remains everywhere else, and the conductive layer is etched in accordance with the photoresist to form source and drain electrodes which are self aligned to the channel insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.