Reduced substrate capacitance high performance SOI process
US6403447B1 · kind B1 · utility
2Cited by
7References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 7, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Jul 7, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor substrate is provided including the general sequential steps of: providing a handle wafer and a device wafer; implanting at least a first impurity region in a first surface of the device wafer; bonding the first surface of the device wafer to a first surface of the handle wafer having a silicon dioxide layer; removing a portion of the device wafer at a second surface; and forming an epitaxial silicon layer on the second surface of the device wafer. The process enables the thickness of the device wafer to be minimal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.