Method of forming a floating gate self-aligned to STI on EEPROM
US6403494B1 · kind B1 · utility
29Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Aug 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.