Trench transistor with superior gate dielectric
US6404007B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100° C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.