Electrically isolated power semiconductor package
US6404065B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 1998 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Sep 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.