Enhanced security semiconductor device, semiconductor circuit arrangement and method or production thereof
US6404217B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1998 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Feb 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31719
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit arrangement providing enhanced security has a first circuitry portion (12) on a semiconductor wafer (10), a second circuitry portion (16) on the wafer separate from the first circuitry portion, the second circuitry portion being coupled (26) to the first circuitry portion and containing access circuitry for allowing access to thereto, and the second circuitry portion being disposed on the wafer such that it can be destructively removed therefrom to leave the first portion of semiconductor circuitry inaccessible through the second portion of semiconductor circuitry. Isolation circuitry (30) is provided for electrically isolating the first circuitry portion following destructive removal of the second circuitry portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.