Chip capacitance measurement circuit
US6404222B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Aug 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2639
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A silicon chip capacitance measurement circuit including three pairs of completely matched MOS transistors divided into two symmetrical circuits. Capacitance of a capacitor within the silicon chip is measured using the difference in average charging current flowing from the measurement circuit via a left and a right capacitor. A power supply provides a constant voltage source to the measurement circuit. A current measuring device measures the current flowing from the power supply to the measurement circuit. A signal generator provides a group of three-phase non-overlapping signals to the measurement circuit. The capacitance measurement circuit is able to limit measurement error due to the return of different size negative currents leading to the transient switching of MOS transistors in the current measurement device so that accuracy of capacitance measurement improves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.