Apparatus and method for interleaving a signal carry chain in an integrated circuit
US6404227B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | May 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interleaved signal carry structure includes a first signal line and a second signal line forming a first bus. A third signal line and a fourth signal line form a second bus. A first set of carry function generators are positioned between the first signal line and the third signal line. Carry-in signal lines are attached to the first set of carry function generators. A second set of carry function generators are positioned between the second signal line and the fourth signal line. Intermediate carry signal lines are positioned between the first set of carry function generators and the second set of carry function generators. Carry out signal lines are attached to the second set of carry function generators. A first vertical carry chain comprises a first carry function generator from the first set of carry function generators and a first carry function generator from the second set of carry function generators. A second vertical carry chain comprises a second carry function generator from the first set of carry function generators and a second carry function generator from the second set of carry function generators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.