System and method for reducing latency in a dynamic circuit
US6404235B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Aug 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic circuit having reduced dynamic node switching latency. The operating status of the dynamic circuit alternates between a pre-charge phase in which a pre-charge device charges the dynamic node, and an evaluation phase in which data at the input of the dynamic circuit may or may not precipitate a dynamic node discharge. Each evaluation phase may be characterized as including an initial standby interval prior to the evaluation discharge, followed by an evaluate interval over which the dynamic node completes an evaluation discharge. A standby device is utilized to drive an output of the dynamic circuit low during a pre-charge phase and to maintain the output low during an standby interval in which dynamic circuit inputs do not result in the dynamic node being discharged. The dynamic circuit includes a standby control circuit that disables the standby device during the evaluation interval, resulting in reduced dynamic node switching capacitance. The dynamic circuit may further include a keeper device connected in parallel with the pre-charge device, wherein the keeper device maintains the dynamic node charged during the standby interval of an evaluation phase. A keeper control …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.