Modified current mirror circuit for BiCMOS application
US6404275B1 · kind B1 · utility
12Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2001 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Nov 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
ESD (Electrostatic Discharge) robust current mirror circuits incorporate circuitry for decoupling the gate when the chip is unpowered. Additional protection is provided by a second element which provides de-biasing to prevent Vgs from being established. A third element can be added between the gate and the ground potential on the current mirror gate node to prevent the gate of the current mirror from rising too high and allows the current to be discharged through the element instead of the current mirror.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.