Twisted bit line structure and method for making same
US6404664B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Sep 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A twisted bit line structure (89) in an integrated memory circuit, and method for making it are presented. The structure is constructed by forming bit line traces (90, 92, 94, 96) on an integrated circuit substrate (88) using phase shift lithography techniques. Using these techniques, the bit line traces are arranged with a plurality of substantially parallel bit lines trace segments (90, 92, 94, 94′, 96, 96′) with discontinuous regions between segments of the interior pair (94, 94′; 96, 96′) of traces. Thus, each “phase &pgr;” bit line trace is adjacent a “phase 0” bit line trace. A first twist connection (102) is formed between first segments (96, 94′) of the center pair of said bit line trace segments at a first height above the level on which the traces are formed, and, and a second twist connection (100) is formed between second segments (94, 96′) of the center pair of said bit line trace segments at a second height above the level on which the traces are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.