Wired address compare circuit and method
US6404682B1 · kind B1 · utility
1Cited by
20References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2001 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Jun 8, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii), a don't care state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.