Memory compiler interface and methodology
US6405160B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1998 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Aug 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compilier methodology including a stand alone memory interface which provides a user specified memory device of a required number of words of memory of a required bits per word. The stand alone memory interface is a tool to provide a menu showing multiple ways in which the user's request can be physically configured by varying the number of rows of memory, the number of blocks of memory, and the column multiplexing factor of the memory array. From this menu the user selects the memory configuration that best meets the user's requirements and is provided with either various models or representations (views) of the selected memory configuration or a GDS format data file. The views can be used to design large scale integrated circuits in which the memory device is embedded while the data file is used to generate photo mask for making the memory device as an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.