Dynamic block processing in a host signal processing modem
US6405268B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host signal processing (HSP) modem or transceiver includes a transmit buffer and a receive buffer. The transmit buffer stores multiple blocks of information representing a transmit signal, and the receive buffer includes available space for multiple blocks of information representing a receive signal. Each block of information corresponds to its respective signal for an associated period that spans the time between consecutive interrupts for the HSP modem. When the host computer fails to service one or more interrupts, the hardware portion of the HSP modem uses the reserve of information from the transmit buffer to generate the transmit signal and stores one or more blocks of information representing the receive signal in the receive buffer. Accordingly, the HSP mode maintains the connection and data throughput even when the host computer misses interrupts. When the host computer services an interrupt, the modem software determines the number of interrupts missed and then dynamically selects the amount of data to process in an attempt to fill the transmit buffer and empty the receive buffer. The amount of information that the modem software processes in response to a single inter…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.