Selectively accessible memory banks for operating in alternately reading or writing modes of operation
US6405293B1 · kind B1 · utility
2Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Mar 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while the other memory bank is being updated from the other interface terminal. The multiplexer circuitry is controlled by a control register which responds to an operation code whereby either memory bank can be updated while the other memory bank is being read for hardware parameters, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.