Microcomputer
US6405302B1 · kind B1 · utility
6Cited by
4References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Apr 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.