Method and apparatus for minimizing semiconductor wafer arcing during semiconductor wafer processing
US6406925B1 · kind B1 · utility
5Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2000 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Nov 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/6833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.