Load insensitive clock source to enable hot swap of a node in a multiprocessor computer system
US6407575B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2000 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | May 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A load-insensitive circuit enables a global reference clock signal source of a synchronous multiprocessor system having a plurality of nodes to be “insensitive” with respect to the insertion or removal (“hot-swap”) of a load (such as a node) when the system is operational. The load insensitive clock source is provided through the use of a customized two-way passive radio frequency power splitter having an input port and two phase-matched output ports. A high degree of isolation is provided between clock signals delivered over the output ports when the input port of the splitter is properly terminated and embedded in a controlled impedance environment. Isolation is further enhanced by terminating each output port with a constant impedance comprising a precisely-matched, 50-ohm impedance load pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.