Digital clock throttling means
US6407595B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.