Apparatus and method for a clock period subdivider
US6407596B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2001 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Apr 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic circuit generates additional clock edges from a reference clock signal utilizing switch-capacitor techniques. The electronic circuit includes a first capacitance circuit and a second capacitance circuit separated by a switch. During a first time period, the switch is open and the first capacitance circuit is charged. During a second time period, the switch is closed and at least a portion of the charge stored in the first capacitance circuit is transferred to the second capacitance circuit. The amount of charge transferred depends upon the relative sizes of the capacitance circuits. During another time period, the second capacitance circuit is discharged until its associated potential reaches a threshold level corresponding to a threshold set by a level detector. Upon reaching the threshold level, the level detector outputs a logic signal. A high frequency clock signal is produced by combining the logic signal with the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.