Mobile communication device having integrated embedded flash and SRAM memory
US6407949B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.