Nonvolatile semiconductor memory device
US6407954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2001 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Feb 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device comprises a plurality of sectors each having a plurality of memory cell arrays, a controller which responds to an address signal and a control signal to activate at least one of the sectors; and a plurality of data comparing circuits provided in the memory cell arrays, respectively, the data comparing circuits each which latches a write data to be written the respective memory cell arrays and compares the write data latched and a data read out from the respective memory cell arrays to produce a comparison result. The controller activates all of the sectors when the control signal has a first logic level regardless of levels of the address signal so that write data is written into the memory cell arrays of the sectors activated. The controller activates the sectors in sequence in response to changing levels of the address signal when the control signal has a second logic level to output the comparison results from the data comparing circuits in sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.