Context switching technique for processors with large register files
US6408325B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 1998 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | May 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system and a method for operating a processor including the steps of establishing a first register save area and a second register save area in a memory, where each register save area holds data values that define a context. The first context is loaded in the processor by loading at least some of the data values from the first register save area into the plurality of registers. A first pointer value to the first register save area is stored in a current RFSA register. A context switch is indicated by storing a second pointer to the second register save area in the current RFSA register. The first pointer is transferred from the current RFSA register to a previous RFSA register. All of the data values that define the first context are transferred from the registers to a shadow register file. The second context is established in the processor by loading selected data values from the second register file save area into the plurality of registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.