Multi-tasking adapter for parallel network applications
US6408341B1 · kind B1 · utility
43Cited by
15References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2000 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Feb 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.