Efficient direct replacement cell fault tolerant architecture
US6408402B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 2000 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Oct 4, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.