High-speed asynchronous decoder circuit for variable-length coded data
US6408421B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a decoder circuit that includes a logic circuit for decoding variable-length coded data coupled to a timing circuit. The logic circuit includes a plurality of computational logic stages, each of the computational logic stages having a synchronization signal input and a completion signal output. Each completion signal output indicates the completion of the computation performed by a computational logic stage. The timing circuit includes a plurality of completion signal inputs and a synchronization signal output, the synchronization signal output being a predetermined function of the completion signal inputs. The completion signal inputs are coupled to the completion signal outputs of the computational logic stages, and the synchronization output is coupled to the synchronization signal inputs of the computational logic stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.