Lamination of circuit sub-elements while assuring registration
US6409930B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1999 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Nov 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process for the formation of an article having multiple electrical circuits comprises:providing a first sub-element comprising in sequence a first metal layer of copper in electrical contact with a second metal layer of aluminum in electrical contact with a third metal layer of copper;etching an electrical circuit design in the first metal layer and in a separate etch step, etching away at least 10%, but less than 100% of the second metal layer to provide electrical connections between the first metal layer and the third metal layer;etching an electrical circuit design into the third metal layer;adhering an etched surface comprising the circuit design of the first or third metal layer to a first surface of a support layer to form a circuit board. The process may etch the first and third metal layers simultaneously or sequentially. After adhering an etched surface comprising the circuit design of the first or third metal layer in registration to a support layer to form a circuit board, an additional step may be performed, which additional step is selected from the group consisting of:a) adhering an etched surface of a second tri-metal subelement to a second surface of the support …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.