Device for the adjustment of circuits after packaging, corresponding fabrication process and induction device

US6410398B1 · kind B1 · utility

Assignee

• STMicroelectronics SA

Inventors

• Christophe Forel · Grenoble, FR
• Sebastien Laville · Grenoble, FR
• Serge Pontarollo · Le Pont-de-Claix, FR

Key dates

• Filing date: Jun 28, 2000
• Grant date: Jun 25, 2002
• Expiry date: Jun 28, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/43

Abstract

A process for forming an electrical resistance in an integrated MOS transistor includes applying a first voltage to the source and gate of the MOS transistor, and applying a second voltage to the drain of the MOS transistor. A prebiasing voltage is applied to the substrate of the MOS transistor to make the base/emitter junction of a parasitic bipolar transistor of the MOS transistor conduct. The first and second voltages are capable of initiating a breakdown of the MOS transistor by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source.