Circuit arrangement with a reduction circuit for reducing interfering longitudinal voltages on a two-wire line
US6410998B1 · kind B1 · utility
1Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2000 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Apr 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/085
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for reducing interfering longitudinal voltages on a two-wire line includes a reduction circuit for reducing the interfering longitudinal voltages, a detector coupled to the two-wire line that generates a switch-off signal in the absence of a push-pull signal on at least one of the cores in the two-wire line and a switch circuit that switches off the reduction circuit in response to the switch-off signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.