Feedback control of clock duty cycle
US6411145B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2001 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Jun 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit configured to correct a duty cycle error or vary the duty cycle of a clock signal. The circuit includes a differential amplifier or control circuit that receives differential signal inputs. At least one differential pair of transistors is connected to outputs of the differential amplifier or control circuit. Outputs of the one or more differential pairs of transistors are connected to inputs of a differential circuit. The differential amplifier or control circuit is connected to the outputs of the differential circuit. The one or more differential pairs of transistors is configured to change a DC level of at least one of the inputs of the differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.