Low jitter external clocking
US6411151B1 · kind B1 · utility
7Cited by
9References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.