Ferroelectric memory device having ferroelectric memory transistors connected to separate well lines
US6411542B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2001 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Oct 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory device including a single ferroelectric transistor that one unit memory cell is independently selected and programmed, when the unit memory cell is programmed for “the first state” or “the second state” by applying a DC bias voltage to the single ferroelectric transistor's gate and well. In addition, the ferroelectric memory device can be applied with normal power level Vdd and GND. The ferroelectric memory device includes a plurality of unit memory cells which are arranged in a matrix, by crossing at least one word line in a column direction with a plurality of bit lines and source lines in a row direction and is connected between the source line and the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.