Semiconductor memory having transistors connected in series
US6411548B1 · kind B1 · utility
135Cited by
5References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Jul 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array is comprised of plural cell units. Each cell unit is connected between a bit line and a source line. Each cell unit is comprised of plural series-connected MFSFETs having substantially the same structure. Of the plural MFSFETs, one MFSFET nearest to the bit line and one MFSFET nearest to the source line are used as select gate transistors. The MFSFETs other than the MFSFETs used as the select gate transistors are used as memory cells. Data is stored in each memory cell as the polarization state of the ferroelectric film of the MFSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.