Device for reducing lock-up time of Frequency synthesizer
US6411660B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 1998 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | May 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J5/0272
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for reducing a lock-up time in a digital cordless telephone. The telephone includes a first frequency synthesizer for generating a reference frequency, a receiver having a first mixer for mixing the reference frequency with an input frequency to generate a first intermediate frequency and a second mixer to generate a second intermediate frequency, and a transmitter having a third mixer to generate a transmission frequency. The device includes: a band switching controller for receiving an inverse channel selection signal; and a second frequency synthesizer for generating third and fourth intermediate frequencies to the second and third mixers, respectively, according to a channel selection signal for setting transmission and reception modes. The second frequency synthesizer includes: a voltage controlled oscillator for generating a frequency according to a charge pump voltage applied at an input of the oscillator; a loop filter for shaping the charge pump voltage being applied to the input of the voltage controlled oscillator; and a phase locked loop for comparing the reference frequency with a frequency output from the voltage controlled oscillator to generate a voltage ac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.